The present invention relates to a motor driving unit provided with at least one pair of arms composed of first and second power switching elements connected in series between main terminals, in particular the present invention relates to a level shift circuit for transmitting a control signal from a low voltage side circuit to a high voltage side circuit, and a power conversion unit having the level shift circuit function.
For energy saving, control of a motor by a semiconductor element such as an IGBT (Insulated Gate Bipolar transistor) has widely been utilized in recent years, by virtue of price reduction of the semiconductor element, in particular, the IGBT.
Incidentally, in the power conversion unit provided with an upper-arm and a lower-arm, because an emitter of the IGBT used in the composing upper-arm is connected to an output, the upper-arm IGBT is driven under a potentially floating state, to a grounding terminal of a main power source. For example, when the upper-arm IGBT is in an ON state, the same high voltage as the main power source is applied. Therefore, to drive the upper-arm IGBT, it is necessary to transmit a signal from low potential to high-potential of a microcomputer which is a control circuit. It is described in JP-3092862 shown in FIG. 15 to use the level shift circuit as a method for sending a drive signal to the potentially floating upper-arm, by the signal from low potential in this way.
Explanation will be given briefly on the operation of the level shift circuit of JP-3092862, with reference to FIG. 15. In FIG. 15, (a), the level shift circuit is composed of two high-voltage n-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, Insulated Gate Field-Effect Transistor) for setting and resetting, two one-shot pulse generators for driving this high-voltage n-type MOSFET, two resistances, a pulse filter and an RS flip-flop. A drain of the high-voltage n-type MOSFET for setting is connected to the resistance and is inputted to the set side of the RS flip-flop through the pulse filter. A drain of the high-voltage n-type MOSFET for resetting is connected to the resistance for resetting and is inputted to the reset side of the RS flip-flop through the pulse filter.
This level shift circuit operates as follows. For the input signal, a pulse is generated from the one-shot pulse generator of the set side for a short period, in rising (input=“L”→“H”) (FIG. 15, (b)). It should be noted that “L” means a low, negative or zero signal. In addition, “H” means a high, positive or 1 signal.
By this pulse, the high-voltage n-type MOSFET of the set side is made ON, and flow of an electric current generates voltage between both ends of the resistance of the set side. By making a time of a pulse generated in the one-shot pulse generator longer than time-constant of the pulse filter, the pulse caused by the voltage generated between the both ends of the resistance passes through the pulse filter, and makes the output ON by setting the RS flip-flop. In falling (input=“H”→“L”), a pulse is generated from the one-shot pulse generator of the reset side for a short period (FIG. 15, (b)), and voltage is generated between both ends of the resistance of the reset side, and makes the output OFF by resetting the RS flip-flop.
In the case where signal transmission is carried out by single high-voltage n-type MOSFET, in a state that the upper-arm is ON, the high-voltage n-type MOSFET is required to be ON under a state that high voltage is applied, which generates very large loss. By splitting the input signal to two signals of setting and resetting, and by demodulation at the RS flip-flop, a time for making the high-voltage n-type MOSFET ON is made short to reduce the loss.
In addition, in JP-3635975, as means for solving the aforesaid problem, a method for using a logic circuit is shown. Explanation will be given on outline of the operation, with reference to FIG. 16. A configuration of two high-voltage n-type MOSFETs for setting and resetting, two one-shot pulse generators that drive the two high-voltage n-type MOSFETs, and two resistances is the same as in FIG. 15. A drain of the high-voltage n-type MOSFET at the set side is inputted to an NAND circuit of the set side through an inverter circuit (NOT circuit, inverting circuit), and further inputted to the NAND circuit of the reset side. A drain of the high-voltage n-type MOSFET at the reset side is inputted to an NAND (non-conjunction) circuit of the reset side through an inverter circuit, and further inputted to the NAND circuit of the set side.
By this configuration, in usual operation, for example, in the case of setting, because a voltage drop is generated only at the resistance of the set side, it is inverted by the inverter circuit to become “H”. Because a voltage drop is not generated at the reset side, it is “H” and a set signal is transmitted to the RS flip-flop. It should be noted that, when voltage variation of the power source (dV/dt, V→V+ΔV) is generated at the high voltage side power source, a voltage drop is generated at both of the set side and the reset side, therefore, for example, the NAND circuit of the set side becomes “H” at the side connected to the resistance of the set side and becomes “L” at the side connected to the reset side, and in this way an erroneous signal is not transmitted to the flip-flop and normal operation is maintained.